EDN

NPTest boosts timing capabilities for SoC tester line

SAN JOSE, Calif. — NPTest Inc., formally known as Schlumberger Semiconductor Solutions, here today announced it has teamed up with GuideTech Inc. and Wavecrest Corp. to bolster its system-on-a-chip ...
T&D

GIS Timing Test with Current Sensor

Andreas Nenning of OMICRON shows a new method for testing the timing of a circuit breaker within a gas-insulated switchgear (GIS). Using this measurement method, both sides of the breaker remain ...
EDN

How to improve async interface testing on ATE

This paper discusses an approach to timing closure to eliminate non-determinism in an asynchronous interface while performing AC characterization on ATE (automatic test equipment). By closing the ...
Electronic Design

A Holistic Approach to Meet Multicore-System Timing and Interference Requirements

How to apply CAST-32A and A(M)C20-193 guidance for heterogeneous multicore processors. Techniques for measuring timing and interference on heterogeneous multicore processors. How to employ robust ...
Electronic Design

Timing Jitter 101

In any system that uses voltage transitions to represent timing information, jitter is an unfortunate part of the equation. In essence, jitter is the deviation of timing edges from their intended ...
Zawya

NPTest Teams with GuideTech to Offer an Integrated Test Solution for Critical Timing Analysis of Graphic Devices and High Speed Buses

15 July 2002 SAN JOSE, California - NPTest, Inc. the wholly owned subsidiary of Schlumberger Limited formerly known as Schlumberger Semiconductor Solutions, introduced today a Critical Timing and ...