September 30, 2014. Keysight Technologies today introduced the DDR Bus Simulator—the industry’s first tool to generate accurate Bit-Error-Rate (BER) contours for the JEDEC DDR memory bus specification ...

DDR verification is one of the most critical and complex tasks in any SoC as it involves a controller sitting inside the DUT and an external DDR memory sitting outside the DUT on board. A DDR system ...

Editor's note: This paper is the third in a series covering the pros and cons of using a Verilog-AMS view with respect to a SPICE view for verification of SOC IP having an analog component. The first ...