Caspia Technologies today announced broad availability of its flagship security verification product CODAx. New and unique capabilities delivered by the product were described, along with its impact ...

While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...

A well thought out design flow for SoCs ensures that the resulting device meets the requirement of low power dissipation. To meet these goals at the device level, individual modules (or components of ...

Siemens Digital Industries Software has launched the Questa One Agentic Toolkit, an AI-driven verification solution designed to accelerate integrated circuit development and RTL sign-off through ...

The complexity of compute-intensive applications is driving the move to system design at the algorithmic level. With the release of the Catapult C synthesis tool, Mentor Graphics now offers the core ...

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...

Given the relative novelty and complexity of RISC-V RTL designs, whether you are buying a commercially supported core or downloading a popular open-source offering, there is the small but non-zero ...

Running quality tests and regression at RTL level, and even fixing all discovered design bugs does not guarantee the flawless hardware design. To make sure there are no bugs in the target hardware, ...