Like many of you, it’s been drilled into me by the Reuse Methodology Manual to write my state machines in VHDL as a pair of processes: a combinatorial process to compute the next state from the inputs ...

Finite State Machines (FSMs) have long been a cornerstone of digital system design, and continuing advancements in logic synthesis have enabled increasingly optimised implementations. At its core, FSM ...

This installment starts a new segment of lessons about state machines. The subject conceptually continues the event-driven theme and is one of my favorites [1,2]. Today, you’ll learn what event-driven ...